(Hong Kong)
Product Summary
The XC2C32 is a low power CPLD. The underlying architecture is a traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Function Blocks of the XC2C32 use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared among any of the macrocells of the FB.
Parametrics
XC2C32 absolute maxing ratings: (1)VCC Supply voltage relative to GND: -0.5V to 2.0V; (2)VI Input voltage relative to GND: 0.5V to 4.0V; (3)TJ Maximum junction temperature: 40℃ to 150℃; (4)TSTR Storage temperature: 65℃ to 150℃.
Features
XC2C32 features: (1)Optimized for 1.8V systems: Industry fastest low power CPLD; Densities from 32 to 512 macrocells; (2)ndustry best 0.18 micron CMOS CPLD: Optimized architecture for effective logic synthesis; Multi-voltage I/O operation: 1.5V to 3.3V; (3)Design entry/verification using Xilinx and industry standard CAE tools; (4)Free software support for all densities using Xilinx WebPACK Industry leading nonvolatile 0.18 micron CMOS process: Guaranteed 1,000 program/erase cycles; Guaranteed 20 year data retention.
Diagrams
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 XC2C32 |
Other |
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Data Sheet |
Negotiable |
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XC2C32A |
Other |
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Data Sheet |
Negotiable |
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XC2C32A-4CPG56C |
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IC CPLD 32MCELL 21 I/O 56-CSBGA |
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XC2C32A-4QFG32C |
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IC CR-II CPLD 32MCELL 32-QFN |
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XC2C32A-4VQG44C |
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IC CPLD 32MCELL 21 I/O 44-VQFP |
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XC2C32A-6CPG56C |
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IC CR-II CPLD 32MCELL 56-BGA |
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XC2C32A-6CPG56I |
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IC CR-II CPLD 32MCELL 56-CSBGA |
Data Sheet |
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XC2C32A-6QFG32C |
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IC CRII CPLD 32MCRCELL 32QFN |
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