CY7C63231A-SC

cy7c63231a-sc, Low-speed USB Peripheral Controller, 70 mA, 300 mW, 0.5V, so

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Price:: US $2.30~2.50 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 100 :	2.50 / Piece
101 ~ 500 :	2.40 / Piece
501 ~ 1000 :	2.30 / Piece

PartNumber:: CY7C63231A-SC

Brand:: Cypress Semiconductor - Cypress | Pack: | D/C:

Availability:: Supply Ability: 8000/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-08-18

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Part Number:CY7C63231A-SC
US $2.30 - 2.50
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Product Summary

The cy7c63231a-sc is a Low-speed USB Peripheral Controller.

Parametrics

cy7c63231a-sc absolute maximum ratings: (1)Storage Temperature: -65℃ to +150℃; (2)Ambient Temperature with Power Applied: -0℃ to +70℃; (3)Supply voltage on VCC relative to VSS: -0.5V to +7.0V; (4)DC Input Voltage: -0.5V to +VCC+0.5V; (5)DC Voltage Applied to Outputs in High Z State: -0.5V to + VCC+0.5V; (6)Maximum Total Sink Output Current into Port 0 and 1 and Pins: 70 mA; (7)Maximum Total Source Output Current into Port 0 and 1 and Pins: 30 mA; (8)Maximum On-chip Power Dissipation on any GPIO Pin: 50 mW; (9)Power Dissipation: 300 mW; (10)Static Discharge Voltage: >2000V; (11)Latch-up Current: >200 mA.

Features

cy7c63231a-sc features: (1)USB D+ and D– lines can also be used for PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be placed in a high-impedance state that will pull up to VCC. (Disable USB by clearing the Address Enable bit of the USB Device Address Register); (2)An interrupt is provided to indicate a long LOW state on the SDATA pin. This eliminates the need to poll this pin to check for PS/2 activity. Refer to Section 19.3 for more details; (3)Internal PS/2 pull-up resistors can be enabled on the SCLK and SDATA lines, so no GPIO pins are required for this task (bit; (4)7, USB Status and Control Register); (5)The controlled slew rate outputs from these pins apply to both USB and PS/2 modes to minimize EMI; (6)The state of the SCLK and SDATA pins can be read, and can be individually driven LOW in an open drain mode. The pins are read at bits [5:4] of Port 2, and are driven with the Control Bits [2:0] of the USB Status and Control Register; (7)The VREG pin can be placed into a high-impedance state, so that a USB pull-up resistor on the D–/SDATA pin will not interfere with PS/2 operation (bit 6, USB Status and Control Register).