(Hong Kong)
Product Summary
The gal20v8b-25ljn is a high performance E2CMOS PLD generic array logic. The gal20v8b-25ljn at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture of the gal20v8b-25ljn provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the gal20v8b-25ljn are the PAL architectures listed in the table of the macrocell description section.
Parametrics
gal20v8b-25ljn absolute maximum ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
gal20v8b-25ljn features: (1)E2 cell technology; (2)Reconfigurable Logic; (3)Reprogrammable Cells; (4)100% Tested/100% Yields; (5)High Speed Electrical Erasure (<100ms); (6)20 Year Data Retention; (7)EIGHT OUTPUT LOGIC MACROCELLS; (8)Maximum Flexibility for Complex Logic Designs; (9)Programmable Output Polarity; (10)Also Emulates 24-pin PALDevices with Full Function/Fuse Map/Parametric Compatibility; (11)PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability.
Diagrams
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 GAL20V8B-25LJN |
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SPLD - Simple Programmable Logic Devices 5V 20 I/O |
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GAL20V8B-25LJNI |
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SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD |
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