D80C187-12

Product Summary

The D80C187-12 is a high-performance math coprocessor that extends the architecture of the 80C186 with floating-point, extended integer, and BCD data types. A computing system that includes the D80C187-12 fully conforms to the IEEE Floating-Point Standard. The D80C187-12 adds over seventy mnemonics to the instruction set of the 80C186, including support for arithmetic, logarithmic, exponential, and trigonometric mathematical operations. The D80C187-12 is implemented with 1.5 micron, high-speed CHMOS III technology and packaged in both a 40-pin CERDIP and a 44-pin PLCC package. The D80C187-12 is upward object-code compatible from the 8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors.

Parametrics

D80C187-12 absolute maximum ratings: (1)Case Temperature Under Bias (TC): 0 to 85℃; (2)Storage Temperature: -65 to 150℃; (3)Voltage on Any Pin with Respect to Ground: -0.5V to VCC+0.5V; (4)Power Dissipation: 1.5W.

Features

D80C187-12 features: (1)High Performance 80-Bit Internal Architecture; (2)Implements ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic; (3)Upward Object-Code Compatible from 8087 Fully Compatible with 387DX and 387SX Math Coprocessors. Implements all 387 Architectural Enhancements over 8087; (4)Directly Interfaces with 80C186 CPU; (5)80C186/80C187 Provide a Software/ Binary Compatible Upgrade from 80186/82188/8087 Systems; (6)Expands 80C186’s Data Types to Include 32-, 64-, 80-Bit Floating-Point, 32-, 64-Bit Integers and 18-Digit BCD Operands; (7)Directly Extends 80C186’s Instruction Set to Trigonometric, Logarithmic, Exponential, and Arithmetic Instructions for All Data Types; (8)Full-Range Transcendental Operations for SINE, COSINE, TANGENT, ARCTANGENT, and LOGARITHM; (9)Built-In Exception Handling; (10)Eight 80-Bit Numeric Registers, Usable as Individually Addressable General Registers or as a Register Stack; (11)Available in 40-Pin CERDIP and 44-Pin PLCC Package.

Diagrams