LC4128ZE-7TN144C

Product Summary

The LC4128ZE-7TN144C is an In-System Programmable Ultra Low Power PLD. The LC4128ZE-7TN144C from Lattice offers an ultra low power CPLD solution. The new family is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the LC4128ZE-7TN144C architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family’s new Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity. The LC4128ZE-7TN144C combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.

Parametrics

LC4128ZE-7TN144C absolute maximum ratings: (1)Supply Voltage (VCC): -0.5 to 2.5V; (2)Output Supply Voltage (VCCO): -0.5 to 4.5V; (3)Input or I/O Tristate Voltage Applied4, 5: -0.5 to 5.5V; (4)Storage Temperature: -65 to 150℃; (5)Junction Temperature (Tj) with Power Applied: -55 to 150℃.

Features

LC4128ZE-7TN144C features: (1)fMAX = 260MHz maximum operating frequency; (2)tPD = 4.4ns propagation delay; (3)Up to four global clock pins with programmable clock polarity control; (4)Up to 80 PTs per output; (5)Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls; (6)Up to four global OE controls; (7)Individual local OE control per I/O pin; (8)Excellent First-Time-Fit and refit; (9)Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders; (10)Standby current as low as 10μA typical; (11)1.8V core; low dynamic power; (12)Operational down to 1.6V VCC; (13)Superior solution for power sensitive consumer applications; (14)Per pin pull-up, pull-down or bus keepercontrol; (15)Power Guard with multiple enable signals.

Diagrams