(Hong Kong)
Product Summary
The MC100LVEP14DTR2G is a low skew 1−to−5 differential , designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the MC100LVEP14DTR2G is operating under PECL conditions. The MC100LVEP14DTR2G specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
Parametrics
MC100LVEP14DTR2G absolute maximum ratings: (1)VCC PECL Mode Power Supply VEE = 0 V: 6 V; (2)VEE NECL Mode Power Supply VCC = 0 V: −6 V; (3)IBB VBB Sink/Source: ± 0.5 mA; (4)TA Operating Temperature Range: −40 to +85 °C; (5)Tstg Storage Temperature Range: −65 to +150 °C.
Features
MC100LVEP14DTR2G features: (1)100 ps Device−to−Device Skew; (2)25 ps Within Device Skew; (3)400 ps Typical Propagation Delay; (4)Maximum Frequency > 2 GHz Typical; (5)The 100 Series Contains Temperature Compensation; (6)PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V; (7)NECL Mode: VCC = 0 V with VEE = −2.375 V to −3.8 V; (8)LVDS Input Compatible; (9)Open Input Default State; (10)Pb−Free Packages are Available.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
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 MC100LVEP14DTR2G |
ON Semiconductor |
Clock Drivers & Distribution 2.5V/3.3V 1:5 Diff ECL/PECL/HST Driver |
Data Sheet |
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| Image | Part No | Mfg | Description | |
Pricing (USD) |
Quantity | ||||||||||||
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Data Sheet |
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Data Sheet |
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Data Sheet |
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ON Semiconductor |
Counter Shift Registers 5V ECL 8-Bit Binary |
Data Sheet |
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Counter Shift Registers 5V ECL 8-Bit Binary Up Synchronous |
Data Sheet |
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MC100E101FN |
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IC GATE OR/NOR QUAD 4INP 28-PLCC |
Data Sheet |
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