(Hong Kong)
Product Summary
The adsp2100akg is an IEEE Floating-Point DSP Microprocessor optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices’ adsp2100akg family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the adsp2100akg has a 30 ns instruction cycle time. With a high-performance on-chip instruction cache, the adsp2100akg can execute every instruction in a single cycle.
Parametrics
adsp2100akg absolute maximum ratings: 1)VIH: 2.0 V; (2)VIHCR: 3.0 V; (3)VIL: 0.8 V; (4)VILC: 0.6 V; (5)VOH: 2.4 V; (6)VOL: 0.4 V; (7)IIH: 10 μA; (8)IIL：10μA; (9)IILT：350 μA; (10)IOZH: 10 μA; (11)IOZL: 10 μA; (12)IDDIN: 490 MA; (13)IDDIDLE: 150 MA; (14)CIN: 10 PF.
Features
adsp2100akg features: (1)Superscalar IEEE Floating-Point Processor; (2)Off-Chip Harvard Architecture Maximizes Signal Processing Performance; (3)30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution; (4)100 MFLOPS Peak, 66 MFLOPS Sustained Performance; (5)1024-Point Complex FFT Benchmark: 0.58 ms; (6)Divide (y/x): 180 ns; (7)Inverse Square Root: 270 ns; (8)32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats; (9)32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators; (10)IEEE Exception Handling with Interrupt on Exception; (11)Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter; (12)Dual Data Address Generators with Indirect, Immedi-ate, Modulo, and Bit Reverse Addressing Modes; (13)Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations; (14)Multiply with Add & Subtract for FFT Butterfly Computation; (15)Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup; (16)Single-Cycle Register File Context Switch; (17)15 (or 25) ns External RAM Access Time for Zero-Wait-State, 30 (or 40) ns Instruction Execution; (18)IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry; (19)223-Pin PGA Package (Ceramic).
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