(Hong Kong)
Product Summary
The cy37256p160-125umb is a High-Performance CPLD. The cy37256p160-125umb provides a range of high-density programmable logic solutions with unparalleled system performance. The cy37256p160-125umb is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features the cy37256p160-125umb’s own product term array, product term allocator, and 16 macrocells. The PIM distributes of the cy37256p160-125umb signals from the logic block outputs and all input pins to the logic block inputs.
Parametrics
cy37256p160-125umb absolute maximum ratings: (1)Storage Temperature: –65 to +150 ℃; (2)Ambient Temperature with Power Applied: –55 to +125 ℃; (3)Supply Voltage to Ground Potential: –0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High-Z State: –0.5V to +7.0V; (5)DC Input Voltage: –0.5V to +7.0V; (6)DC Program Voltage: 4.5 to 5.5V; (7)Current into Outputs: 16 mA; (8)Static Discharge Voltage: ＞2001V; (9)Latch-up Current: ＞200 mA.
Features
cy37256p160-125umb features: (1)In-System Reprogrammable (ISR) CMOS CPLDs; (2)High density 32 to 512 macrocells; (3)Simple timing model; (4)3.3V and 5V versions; (5)PCI-compatible[1]; (6)Programmable bus-hold capabilities on all I/Os; (7)Intelligent product term allocator provides: 0 to 16 product terms to any macrocell; (8)Flexible clocking Four synchronous clocks per device; (9)Consistent package/pinout offering across all densities; (10)Packages: 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages.
Diagrams
