(Hong Kong)
Product Summary
The cy7c342b-35ri is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. The 128 macrocells in the cy7c342b-35ri is divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of thecy7c342b-35ri allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the cy7c342b-35ri allows the replacement of over 50 TTL devices. By replacing large amounts of logic, it reduces board space, part count, and increases system reliability.
Parametrics
cy7c342b-35ri absolute maximum ratings: (1)Storage Temperature: –65℃ to +135℃; (2)Ambient Temperature with Power Applied: –65℃ to +135℃; (3)Maximum Junction Temperature (under bias): 150℃; (4)Supply Voltage to Ground Potential: –2.0V to +7.0V; (5)DC Output Current per Pin: –25 mA to +25 mA; (6)DC Input Voltage: –2.0V to +7.0V; (7)Operating Ambient Temperature Range: Commercial 0℃ to +70℃, Industrial –40°C to +85°C; (8)VCC: Commercial 5V ± 5%, Industrial 5V ± 10%.
Features
cy7c342b-35ri features: (1)128 macrocells in eight logic array blocks (LABs); (2)Eight dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array; (3)Advanced 0.65-micron CMOS technology to increase performance; (4)Available in 68-pin HLCC, PLCC, and PGA packages.
Diagrams
