LC4384V-10T176I

Product Summary

The LC4384V-10T176I is a member of the ispMACH 4000V family from Lattice which offers a SuperFAST CPLD solution. It is a blend of Lattice’s two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families, the LC4384V-10T176I architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family. The LC4384V-10T176I combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, it delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration. The LC4384V-10T176I offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls. The LC4384V-10T176I has enhanced system integration capabilities. It supports 3.3V supply voltage and 3.3V interface voltage. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LC4384V-10T176I also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LC4384V-10T176I is 3.3V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment.

Parametrics

LC4384V-10T176I absolute maximum ratings: (1)Supply Voltage (VCC): -0.5 to 5.5V; (2)Output Supply Voltage (VCCO): -0.5 to 4.5V; (3)Input or I/O Tristate Voltage Applied: -0.5 to 5.5V; (4)Storage Temperature: -65 to 150℃; (5)Junction Temperature (Tj) with Power Applied: -55 to 150℃.

Features

LC4384V-10T176I features: (1)High Performance; (2)fMAX = 400MHz maximum operating frequency; (3)tPD = 2.5ns propagation delay; (4)Up to four global clock pins with programmable clock polarity control; (5)Up to 80 PTs per output; (6)Ease of Design; (7)Enhanced macrocells with individual clock, reset, preset and clock enable controls; (8)Up to four global OE controls; (9)Individual local OE control per I/O pin; (10)Excellent First-Time-FitTM and refit; (11)Fast path, SpeedLockingTM Path, and wide-PT path; (12)Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders; (13)Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C): 1.8V core low dynamic power; (14)Broad Device Offering Multiple temperature range support: Commercial: 0 to 90℃ junction (Tj), Industrial: -40 to 105℃ junction (Tj), Automotive: -40 to 130℃ junction (Tj); (15)Easy System Integration; (16)Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O; (17)Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies; (18)5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces; (19)Hot-socketing; (20)Open-drain capability; (21)Input pull-up, pull-down or bus-keeper; (22)Programmable output slew rate; (23)3.3V PCI compatible; (24)IEEE 1149.1 boundary scan testable; (25)3.3V/2.5V/1.8V In-System Programmable (ISP using IEEE 1532 compliant interface; (26)I/O pins with fast setup path.

Diagrams