(Hong Kong)
Product Summary
The ql3004e-1pf100c is a pASIC 3 FPGA fabricated on a 0.35 µm four-layer metal process using QuickLogic s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.The ql3004e-1pf100c contains a range of 96 to 1,584 logic cells. With a range of 74 to 316 I/Os, the pASIC 3 family is available in many device/package combinations. Software support for the complete the ql3004e-1pf100c is available through two basic packages. The turnkey QuickWorkspackage provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar TM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
Parametrics
ql3004e-1pf100c absolute maximum ratings: (1)VCC Voltage: -0.5 V to 4.6 V; (2)VCCIO Voltage: -0.5 V to 7.0 V; (3)Input Voltage: -0.5 V to VCCIO +0.5 V; (4)Latch-up Immunity: ±200 mA; (5)DC Input Current: ±20 mA; (6)ESD Pad Protection: ±2000 V; (7)Storage Temperature: -65°C to +150°C; (8)Lead Temperature: 300°C.
Features
ql3004e-1pf100c features: (1)Interfaces with 3.3 V and 5.0 V devices; (2)PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades; (3)Full JTAG boundary scan; (4)I/O cells with individually controlled registered input path and output enables; (5)Input + logic cell + output total delays under 6 ns; (6)Data path speeds over 400 MHz; (7)Counter speeds over 300 MHz; (8)Up to 60,000 usable PLD gates with up to 316I/Os; (9)300 MHz 16-bit counters, 400 MHz datapaths; (10)0.35 μm four-layer metal non-volatile CMOS process for smallest die sizes.
Diagrams
